1. Field of the Invention
The present invention relates to semiconductor technology, and in particular to a method for fabricating an interconnect structure with air gaps for a semiconductor device that reduces capacitance between interconnects while maintaining the mechanical strength of the interconnect structure.
2. Description of the Related Art
Production of smaller semiconductor devices on a chip is a key technology for the next generation of integrated circuits. As the downscaling of device dimensions continues, the distance between conductive interconnects is reduced to increase the integration density. The reduced dimensions of the interconnect necessitates that dielectric materials disposed between the conductive elements, have a lower dielectric constant (K) than previously utilized, due to the capacitive coupling between adjacent conductive elements in an integrated circuit (IC).
A reduced distance between the conductive elements, however, generates parasitic capacitance which undesirably increases time constant (RC) delay and power consumption in an IC, wherein R is the resistance and C is the capacitance of the IC. In order to achieve high speed, low power consumption ICs, parasitic capacitance must be reduced in an IC. As the device and interconnect density increases, parasitic capacitance becomes a significant problem. Although current low K dielectric materials can provide a K value of less than 4.0, materials having a lower K value are still required in order, to support the continued reduction in device dimensions and increased circuit density.
A common method utilized to form the interconnect structure in a semiconductor device is a damascene or dual damascene process. In this method, one or more low K dielectric layers is deposited on a substrate and patterned by lithography and etching, to form openings, such as trenches, via holes, or contact holes, for filling of conductive materials therein to serve as the interconnect. During stripping the photoresist mask which is utilized to define the low K dielectric layers, however, the sidewalls of openings may be damaged due to oxygen plasma stripping, causing a damage zone with a K value of more than that of the undamaged low K dielectric layer. As a result, undesirable parasitic capacitance between the conductive elements is increased.
Thus, there exists a need in the art for development of an improved method for fabricating an interconnect structure in a semiconductor device which can reduce capacitance between interconnects.